PCIe Compliance Testing & Solutions

GRL’s team has a deep history in PCIe supporting PCI-SIG committees, workshops, and adopters across the ecosystem. Offering include compliance and debug.

PCIe 5.0, 4.0 and earlier Base (ASIC) and CEM (System) Specification Pre-Compliance & Characterization for IC’s, End Point (device), Root Complex (Host/System), Backplanes, and Connectors:

Transmitter & Receiver LinkEQ Electricals & Rx Jitter Margin
Tx Pre-emphasis Level Verification & RefClk Jitter
Return Loss/Insertion Loss
PLL Peaking and Bandwidth
Transaction & Link Layer (PTC)
Configuration Space (CV)
PCIe Protocol Layer Analysis, Debugging & Stress Testing

PCIe Integrators List (IL) Certification is available only at the PCI-SIG workshops. Work with GRL to ensure compliance before you attend the workshop, or debug compliance-related issues.

Besides PCIe BASE and CEM form factor, the testing can be done on the following form factors:

U.2
U.3
M.2
EDSFF
miniSAS
Custom connectors

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