Signal & Power Integrity Analysis Test Labs

Refine electrical and signaling routes using GRL's full range of signal & power integrity test services and solutions.

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What is signal integrity?

Signal integrity measures the degree to which a signal can be propagated from transmitter to receiver without distortion. Environmental factors that can disrupt signals during the traveling process include:

  • Crosstalk
  • Ground bounce
  • Jitter
  • Mismatch
  • Reflections
  • Ringing

Why signal integrity is important in printed circuit boards (PCB)

Special care is required to minimize environmental influence on signal integrity. As an essential component of many electronic devices, printed circuit boards (PCBs) are prominent green plates made of an insulating fiberglass component and conducting copper metal tracks. Because high signaling speeds are often bottlenecked at PCBs, signal integrity analysis is often used to design and reconfigure PCBs until they can transmit signals quickly and reliably.

Signal integrity test and analysis

Signal integrity tests can be conducted by creating signals between transmitter and receiver models under controlled environments. When analyzing signal integrity, it is important to ensure that the following factors do not influence test results:

  1. Bridged to signal plates
  2. Device Under Test (DUT) welding angle
  3. Measuring methods
  4. Signal-adopted line length
  5. Surrounding element interference
  6. Testing point

Causes of signaling issues can be narrowed down by examining signal quality, crosstalk, and timing. 

VNA and TDR analysis in signal integrity

VNA and TDR are digital signal integrity measurements. VNA is measured by sweeping sine waves through narrow band filters to scan transmitters and receivers in a synchronized fashion. From there, information on frequency domain performance (S-parameters) and system losses (insertion and return loss) can be retrieved. VNA data must be converted into time domain using additional software in order to gain further insight into DUT topology.

TDR is measured using instruments that consist of a wide bandwidth equivalent sampling oscilloscope and an internal step generator that sends signals to the DUT. TDR analysis enables designers to measure DUT properties such as location of failures, impedance, time delay, and system topology. More properties such as crosstalk, rise time degradation, return loss, skin effect, and dielectric loss can also be measured using Time Domain Transmission (TDT). Due to the transient nature of this measurement technique, TDR results are visual and intuitive. Additional software is usually required for frequency dependent behavior observation.

What is power integrity?

Power integrity refers to current that runs through drivers and receivers. This current has to remain stable in order for signals to be sent and received reliably. As such, power integrity can be considered a subset of signal integrity. Both signal integrity and power integrity are integral to proper analog operation within digital circuits.

Power integrity issues primarily stem from voltage ripple noise, which is created when transients react with channel inductance. Current transients are in turn generated when AC sources are converted to DC rails. Because every component is connected to the main power supply, ripple noise can transfer to and affect any part of a system via crosstalk.

Electromagnetic interference (EMI) from unfiltered AC power sources are another common source of power integrity disruption. Without proper design, EMI can influence wireless signals and cause crosstalks to crop up during electromagnetic compatibility (EMC) testing for regulatory compliance.

Power integrity test and analysis

Power integrity analysis involves the identification of DC power rail disruptions and EMI issues to ensure that sufficient current can be transmitted steadily through devices so that they work as intended. 

Parameters for power integrity testing can be difficult to define as they depend on signal integrity components. Additionally, higher-frequency energy moves in both x and y directions as it is distributed through transmission planes, further adding to analysis complexity. 

While analysis at DC levels only requires series resistances of traces, plane shapes, and vias to be calculated, additional factors such as board location, mounting method, as well as the positioning, type and value of capacitor have to be considered at higher frequencies. 

PCB design guide


Vias are plated-through holes in PCBs used to trace a board’s surface layer to both inner and outer layers. PCB vias can be drilled mechanically and plated to create electrical connections, and consist of the following components:

  • Barrel: Conductive tubes that fill percolated holes.
  • Pads: Links barrel ends to traces.
  • Antipads: Clearance holes that separate barrels and non-connective layers.

In multi-layered boards, vias create routes for electrical and thermal current flow between layers, with the amount of current varying based on via size and type. Types of vias include:

  • Through-hole via: The most common type of via
  • Blind via: Cannot be seen on other parts of the PCB. Used to connect the board's surface layer to subsequent layers.
  • Buried via: Cannot be seen on the surface of the PCB. Used to link inner layers of a board.  

Layer stacking

PCB layer stacking plays a vital role in determining signal integrity. Careful layer organization prevents impedances that generate common-mode currents, which in turn produce RF energy. Once RF energy enters power distribution networks or free spaces, it will emit noise that produces signal disrupting reflections, ringing, or crosstalk.

On the flipside, proper PCB layer stacking can incorporate features that are conducive for maintaining signal integrity. For example, high-speed traces can be striplined to maximize both shielding and inner layer flux cancellation with adjacent ground plates. Less sensitive traces can also be microstriped on outer PCB layers due to their low risk for coupling through the air. 

Trace routing

Trace routing comes after via and layer stacking have been finalized and is closely tied to how PCB components are positioned. For instance, escape routing must be carefully designed to ensure that all signals are connected and that associated components like bypass caps are as close to their pins as possible. 

Common trace routing best practices include:

  • Always keep signal path traces as short and direct as possible.
  • Avoid routing sensitive signals through crowded parts of the circuitry, such as analogs or power supply sections.
  • Leaving sufficient room for specific routing topologies wherever necessary.
  • Minimizing vias to avoid length and inductance that may introduce more signal integrity problems further down the road.
  • Separating sensitive high-speed signals such as clock lines from other traces as far as possible. A minimum of three times the trace width should be used. 
  • Tie differential pairs routed tightly together, do not split the pair around obstacles like vias. 
  • Whenever routing groups of nets that must be equal in length, begin with the longest connection first, adding tuning turns to the rest until all nets reach equal length.