Rapid moving data makes the digitalized world go round
Bandwidth demands in the automation age
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Network traffic is more saturated than ever before. Rapid adoption of increasingly sophisticated artificial intelligence (AI) and machine learning (ML) applications have multiplied the cloud-based workloads exponentially, creating an insatiable demand for more bandwidth to support the acceleration of high speed networking protocols. This means that the historical trend of speeds doubling every 2-3 years might be set to climb even higher in the automation age.
Halved latency, doubled speed, limitless possibility
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Performance levels required to facilitate AI and ML technology can be facilitated by the latest PCI Express® (PCIe®) standard, the PCIe 6.0 specification. Providing a high performance bandwidth of 64.0 GT/s, PCIe 6.0 doubles the data transfer rate of the previous PCIe 5.0 to provide the low latency required for eliminating bottlenecks and allowing real-time applications and services to perform optimally.
Staying ahead of heightened market demand
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PCIe 6.0 is yet another example of how PCI-SIGR continues to deliver industry-leading specifications that help test engineers stay ahead of market demand for higher bandwidths and lower latencies required for increasingly computer intensive systems. As the digitalization wave continues to overtake industries, the need for speed will inevitably be witnessed throughout data centers, high-performance computing (HPC), storage applications, and other market segments in increasing magnitudes.
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PCIe® 6.0: The next frontier of AI and ML applications
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PCI-SIG® is an electronics industry consortium that defines PCIe® I/O bus specifications related to form factors. Featuring a twelve year high membership base of 900 companies, PCI-SIG continues to push out data transfer trusted specifications and mechanisms to support compliance and interoperability.
Having doubled data transfer rates with each installation of PCIe since PCIe 2.0, the high-speed serial computer expansion bus standard has come a long way since the 2.5Gb/s days of PCIe 1.0 way back in 2003. These advancements are only possible thanks to efficient improvements in the coding scheme and single modulation changes, such as the critical employment of PAM4 signal in PCIe 6.0 that enables doubled data rate with no increase in clock rate from PCIe 5.0.
PCle® Technology benefits
- Double Bandwidth: Increases the data rate to 64 GT/s, double the PCle 5.0 specification data rate with maximum bidirectional bandwidth of up to 256 Gb/s for x16 lanes
- Low Latency: By Utilizes Flow Control Units with fixed size (Flits) enabling lightweight FEC (forward error correction) with PAM4 signaling and CRC (cyclic redundancy check) with no latency impact
- Backwards compatible: Maintains compatibility with previous generations of PCle 5.0, 4.0, 3.0, 2.0, and 1.0 technology
- Low Power State: Allows traffic to run on a reduced number of lanes to save power. This is a critical feature. Maintains at least one active lane at all times to allow uninterrupted traffic flow.
AI and ML market use cases for PCle® Technology
As an increasing proportion of enterprises migrate workloads on to the cloud, data center manufacturers are focusing more attention onto AI and ML workloads to build singular computers that can execute multiple processes. The integration of AI and ML is inseparable from large computing horsepower and storage space required to support future data transfer demands. PCIe makes all this possible by forming an interface backbone that moves high bandwidth data between CPUs, GPUs, and other nodes. In other words, the PCIe6.0 architecture forms a critical bridge between CPUs and AI accelerators.
Architecture Design Challenges
The following architectural challenges need to be overcome to ensure that the system is designed as it should be and the system works as expected:
- SI simulation to deal with complicated system design using equalizers, re- driver and lossy connector/channel and to maintain reasonably low BER regardless of PAM4 modulation
- Electrical Validation to make sure that the signal integrity is achieved as expected (electrical performance, error rate, equalization settings, etc.)
- Functional Validation to check if the performance meets expectations (Although FEC and CRC is implemented, if "Retry" happens often performance goes down).
Signal Equalization
More selections in equalizer settings are available in PCIe 6.0 specification
Re-timer use case
Difference between re-timer and re-driver
Re-timer supports the system which has a long channel. It’s important to note that up to 2 re-timers can be used between root complex and device.
PAM4 modulation
While NRZ has 1 bit per 1 clock cycle, PAM4 has 2bits per 1 clock cycle. In addition, PAM4 has a worse signal-to-noise ratio compared to NRZ, but has a higher BER expected than NRZ’s 10E-12 BER.
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