IC Characterization and PHY Tuning

Overcome the most common challenges in IC characterization, PHY tuning, and semiconductor testing at GRL's test center of excellence.

GRL: A Center of Excellence in IC Characterization

Our background

GRL’s engineers hail from rich backgrounds in IC validation, PHY design, and test equipment, and have been developing and executing test plans for IC companies that require characterization, stress testing, and PHY tuning services since the company was built in Silicon Valley in 2010.

Priding ourselves as a Center of Excellence, GRL is proud to provide industry leading IC characterization and tuning services across labs in Silicon Valley, Taiwan, Japan, China, and India. Our comprehensive characterization services for early silicon ranges from 112 Gb/s PAM-4 (copper and optical), to sub-gigahertz custom memory interfaces, and specialized analog and mixed-signal ICs (AFE, ADC, DAC, sensors).

Your test process

We curate extensive test processes that cover all types of test objectives and budget needs: 

  1. Assign technical experts to the project
  2. Develop custom test methodologies
  3. Develop custom test automation
  4. “Audit” IP vendor silicon
  5. Consult on characterization board design & layout
  6. Perform SI simulation and measurements on characterization boards
  7. Procure or develop custom test accessories
  8. Perform debugging and PHY tuning on the first silicon
  9. Perform higher volume bench characterization over multiple PVT corners
  10. Provide turnkey characterization test setup in customer’s lab using GRL’s Test Automation Framework

Through this customizable approach, companies only have to pay for what they use, and can avoid expenses associated with fixed rates and maintenance of obsolete equipment. GRL hopes to cushion our clients against the rising cost of testing while also improving access to specialized technical experts and high-performance test equipment via an on-demand basis. 

Importance of stress testing

IC stress testing conducted on high-speed interface_crocodile clip wires_process, voltage, temperature (PVT) corners

Today, semiconductor companies face enormous challenges in validating their high-speed interfaces. Not only must they account for interfaces that are becoming faster and incorporating more complicated power management features, they must also support an increasing number of new interfaces every year and rising customer demands for characterization reports. 

As process nodes shrink, engineers find themselves dealing with increased PVT sensitivity, which must be thoroughly understood in high pressure environments where timelines and budgets are tight.

IC stress testing VS compliance certification testing

Unlike compliance certification testing where the objective is to pass within the shortest time possible, IC stress testing requires semiconductor companies to monitor the performance of high-speed interfaces under a variety of non-ideal environments. Examples include extreme temperatures, supply voltages, as well as fast and slow process corners. Moreover, signal integrity issues stemming from the following sources also have to be accounted for:

  • Board design mistakes
  • Interference from clock or other components
  • Noise
  • Packaging that introduces waveform impairments resulting in:
    • Excessive jitter
    • Inter-Symbol Interference (ISI) effects

Common semiconductor challenges

On top of dealing with their own ICs and reference designs, semiconductor companies must address issues of interoperability with other ICs and systems. This problem is further complicated by the fact that other ICs may not always have optimal operating margins. It is not uncommon for semiconductor companies to encounter roadblocks when the ICs of other vendors fail to meet compliance specifications. To make matters worse, the responsibility of compliance and interoperability often falls upon the IC vendor, even when issues stem from customer system design. 

Adding to the challenge of interface design complexity is the excessive reliance on external IPs that may not be fully tested or correctly implemented. Furthermore, SERDES and PHY transceiver designs are also becoming increasingly specialized. Validating these external IPs and resolving debugging issues as they arrive can therefore result in significant delays. Given the high cost of IC masks and short time to market windows, re-spins can prove critical in terms of both budget and labor.

To adapt to these challenges, semiconductor companies should operate with the mindset of “test to fail” so that design issues can be resolved and performance margins can be maximized. Without spending weeks or even months to properly tune interface designs, ICs (particularly those at lower process nodes) will likely fail to meet even 30% of compliance specs PVT variations.