As part of the PCI-SIG defined PCIe 6.0 electrical compliance criteria for 64 GT/s, the PCI Express Card Electromechanical (CEM) 6.0 Specification and PCIe 6.0 PHY Test Specification details how transmitter (Tx) measurements, receiver (Rx) measurements, and other electrical parameters need to be measured. Let's take a closer look at what the Rx and Tx Link Equalization test setup and requirements are.
PCIe® 6.0 CEM Receiver (Rx) test equipment requirements
High-performance oscilloscopes of ≥ 50 GHz bandwidth are required to accurately perform stressed Eye Calibration for the PCIe 6.0 CEM Receiver (Rx) compliance testing. The process can be smoothened with PCIe 6.0 CEM automation software like the GRL-PXE6-CEM-RXA software, which can be used with BERTs and real-time oscilloscopes to shorten equipment calibration and test time.
For Rx and Tx Link Equalization testing, a high-performance, protocol aware Bit Error Rate Tester (BERT) capable of Link Training and pattern generation can be used to force a Device Under Test (DUT) into a loopback through Recovery State within LTSSM State Machine. Finally, it's important to ensure that all coaxial cables used in the setup are of proper bandwidth and phase matched with <1ps skew.
Test equipment summary:
- High-performance oscilloscopes of ≥ 50 GHz bandwidth
- PCIe 6.0 CEM automation software (e.g. GRL-PXE6-CEM-RXA)
- Protocol aware, high-performance BERT
- Phase matched 2.92mm or 2.4mm cables
PCIe® 6.0 CEM Rx test setup requirements
PCI-SIG Gen6 Compliance Test fixture is required to be used to perform CEM Compliance Testing. The SIG Compliance Test fixture kit will consist of the following items: Compliance Load Board (CLB), Compliance Base Board (CBB), Variable ISI Board and various Cable sets. These boards and cables will be used to calibrate, validate and later test for the PCIe Gen6 Receiver Compliance using BERT and High Bandwidth Oscilloscope.
Test setup summary:
- PCI-SIG Compliance Load Board (CLB): For calibration and testing Host/System topology
- PCI-SIG Compliance Base Board (CBB): For calibration and testing Add-in card topology
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PCIe 6.0 CEM Rx Link Equalization testing reference diagrams
Examples of PCIe 6.0 CEM Rx calibration setup.
The Gen6 Compliance Test fixtures must be characterized using ENA to identify required ISI channel to be used based on testing topology. Calibration of the Stressed Eye pattern sent to DUT must be completed before PCIe 6.0 CEM receiver testing, and it is done in two (2) steps. The first step is calibration to TP3. The second is done to TP2 (Long Channel) test points according to the following parameters:
TP3 calibration
- Initial preset Q0
- Launch amplitude
- Pre-shoot and de-emphasis
- Preset, RJ and SJ
TP2 (long channel) calibration
- DM, CM
- Final Stressed Eye Calibration (Eye Width and Eye Opening)
While automation sets and tunes all required parameters, the postprocessing is done on the background by the SigTool for (CEM Specification) or Seasim for (Base Specification) for validating Final Stressed Eye. The same procedure can be done manually and will easily take several days to complete due to parameter value combinations and retesting. For any change in Final Stressed Eye setup requires recalibration. For this reason, automation via the GRL PCI Express 6.0 Receiver Test Automation Software Suite (GRL-PXE6-RXA) for PCIe 6.0 Host and Add-In Card designs are highly recommended.
DUT Link Equalization, Compliance Testing
Rx and Tx Link Equalization testing is performed at 64.0 GT/s over several tests which will include:
- Initial Tx Equalization Test
- Tx Link Equalization Response Time test
- Tx Link Equalization Coefficient test
- Rx Link Equalization test
As with calibration, the testing process automation is highly recommended as the equipment will automatically be configured to required settings and Link Train the DUT into the required Loopback for testing itself.
Examples of PCIe 6.0 CEM TxRx link equalization test setup.
To prepare a DUT for testing and loopback state, the automation solution will configure a BERT to perform Link Training with DUT into L0 State followed by entry into Recovery State. Once in Recovery State the DUT will enter Loopback State with LTSSM State Machine and ready for testing. Measurements of the First Bit Error Ratio (FBER) will then be taken using Calibrated Stressed Eye signal through the Rx path to ensure a FBER of 1E-6 or better can be achieved.
Examples of PCIe 6.0 CEM Rx compliance test setup.
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