PCIe® 8.0 by 2028: Preparing for 256 GT/s and High-Bandwidth Computing

On August 5, 2025, PCI-SIG officially announced the PCI Express® (PCIe®) 8.0 specification¹ — a major milestone that continues the long-standing tradition of doubling PCIe® bandwidth every three years. With a raw bit rate of 256.0 GT/s and up to 1 TB/s of total bi-directional throughput over a x16 configuration, PCI-SIG is setting the stage for a new era of high-speed data interconnects in compute-intensive environments.

Building on PCIe 7.0 to future bandwidth demands

The announcement comes mere months after the release of PCIe 7.0, reinforcing PCI-SIG’s commitment to scaling performance in step with market demand for AI, ML, high speed networking, and advanced computing workloads.

In response to increasing pressure on I/O interconnects to deliver both speed and efficiency, PCIe 8.0 aims to advance raw performance while balancing latency and system scalability by working towards the following goals:

Doubling throughput over PCIe 7.0 to 256 GT/s per lane
Confirming latency and FEC performance targets are met
Enhancing bandwidth utilization through protocol improvements
Maintaining backwards compatibility with earlier PCIe generations
Improving power efficiency, which has become a critical design constraint
Reviewing new connector technologies to support signal integrity and scalability

Overcoming physical layer limitations for PCIe 8.0

Nevertheless, some hurdles must be overcome on the road to 256.0 GT/s raw bit rate and 1 TB/s bi-directionally via x16 configuration. PCIe 8.0 specification is expected to continue leveraging PAM4 signaling, Flit Mode encoding, and forward error correction (FEC) introduced in PCIe 6.0 and 7.0. However, achieving these speeds over copper traces that span tens of centimeters on motherboards pushes the boundaries of current signal integrity techniques. PCI-SIG is now evaluating new interconnect approaches that can support this level of performance while ensuring acceptable signal-to-noise ratios, minimizing insertion loss, and preserving power efficiency.

Sustained industry demand for AI/ML, HPC, and Edge Drive

The PCIe® roadmap remains tightly aligned with the industry's growth trajectory. Data center networks are actively deploying PCIe 6.0 solutions and have already expressed strong interest in PCIe 7.0. A growing list of applications are already expected to be served by PCIe 8.0, including:

Artificial Intelligence / Machine Learning (AI/ML)
Edge computing
Quantum computing
High-performance computing (HPC)
Hyperscale data centers
Automotive and aerospace systems

At the same time, the global PCIe® retimer market is well primed for expansion, with a projected CAGR 10.7% taking total valuation from USD 61.36 million in 2024 to over USD 1 billion by 2029².

Building the foundation for PCIe 7.0, 8.0, and beyond

Companies building next-generation platforms can ensure that their products meet current specifications while preparing for upcoming transitions by ensuring that they fulfil PCIe 6.0 criteria that is shaping today’s designs.

As the first PCIe® Authorized Test Lab to provide official PCIe 5.0 and 4.0 compliance testing, Granite River Labs (GRL) boasts an extensive history in supporting PCI-SIG committees, workshops, and adopters across the ecosystem.

GRL PCIe test services

Today, we offer:

PCIe 4.0 and 5.0 (to 16GT/s) Official Compliance Testing and Integrators List Certification for Add-in Cards (devices) and Systems (hosts).
PCIe 6.0, 5.0, 4.0 and earlier Base (ASIC) and CEM (System) Specification Pre-Compliance & Characterization for IC’s, End Point (device), Root Complex (Host/System), Backplanes, and Connectors

Check out our official PCIe® services page for more details.

GRL PCIe test solutions

GRL is also proud to support this evolution by offering industry-leading PCIe® 6.0 Base and CEM Receiver Test Automation Solutions (GRL-PXE6-RXA), which comes with support for the Anritsu MP1900A BERT (GRL-PXE6-RXA). Featured at the PCI-SIG® Developers Conference 2024, the GRL-PXE6-RXA simplifies PCIe 6.0 specification compliance testing using silicon-proven Synopsys IP for PCIe 6.x.

Reach out to our engineers for a consultation today.