Jan 17, 2024 GRL Team

GRL & Teledyne LeCroy present: Demystifying PCIe® Electrical, Link and Protocol Design & Test

Advanced PCIe webinar event page
Session 1 
Date: February 6, 2024 (Tuesday) 
Time: 09:00 PT | 18:00 CET | 22:30 IST
Session 2 
Date: February 7, 2024 (Wednesday) 
Time: 07:00 PT | 16:00 CET | 20:30 IST 


Eugene Sushansky - Vice President of Global Engineering, Granite River Labs
Gordon Getty - Staff Product Marketing Manager, Teledyne LeCroy Austin Labs

Wesley Mason - Program Manager, Test and Compliance, Teledyne LeCroy Austin Labs

Catch our webinar "Demystifying PCIe® Electrical, Link and Protocol Design & Test"

PCI Express® (PCIe®) has become the interconnect of choice for data-intensive applications like data center, AI/machine learning, HPC, automotive, IoT, and military/aerospace.

Delivered by experts from recognized PCIe leaders GRL and Teledyne LeCroy - Austin Labs, this webinar will delve into the intricacies of PCIe® Electrical, Link and Protocol Design & Test. We will focus on PCIe 5.0 and 6.0 while looking ahead to 7.0, and examine Compute Express Link (CXL) which leverages PCIe. We aim to provide you with not only a clearer understanding of PCIe specifications but also practical knowledge through case studies and an opportunity for Q&A. We hope this webinar will better equip you to navigate the complexities of PCIe design and testing.

Who should attend?

This webinar is designed for any engineers working with PCIe, especially chip and system developers for data center, enterprise storage, and cloud/AI/HPC applications. If you're experienced in PCIe technology and ready to dive deeper into PCIe design and testing, come join us.

In this webinar, you will learn about:

  • PCIe overview and design considerations
    • Base vs CEM specifications
    • Reference channel and EQ considerations
    • Design for testability – addressing the “gotchas” including CEM and test board design
  • PCIe compliance test requirements overview – Base vs CEM
    • Electrical and link equalization
    • Link and transaction layer
    • Lane margining
    • Config space and interoperability
    • Certification / Integrator List requirements
  • Electrical & link EQ setup considerations and pitfalls
    • Calibration, test channel characterization, form factors & fixtures, etc.
    • Debugging case study
    • When “testing by the book” isn’t practical – case study for embedded / chip-to-chip
  • Link, transaction and system layer design and test
    • Design and test considerations
    • Test and debugging solutions
    • PCIe system performance analysis and benchmarking
    • CXL: what is it, how does it leverage PCIe, and why should you care
  • and more!


Note: If you are unable to join any of the webinar sessions, please also sign up on the registration page and we will send you the recording after the webinar ends.  

Published by GRL Team January 17, 2024