Jan 30, 2024 GRL Team

Understanding and Optimizing Equalizers (EQ) in PCI Express® (PCIe®)—Technical Webinar

SI PCIe webinar event page
Session 1 
Date: March 19, 2024 (Tuesday) 
Time: 09:00 PT | 18:00 CET | 22:30 IST
Session 2 
Date: March 20, 2024 (Wednesday) 
Time: 07:00 PT | 16:00 CET | 20:30 IST


Miki Takahashi - Executive Vice President of Engineering, Granite River Labs
Miki is an expert in SERDES design, SD Interfaces (UHS-1, UHS-2), CF Interfaces (CFast, XQD), and JEDEC (DDR, UFS). He currently Chairs the SD Card Association UHS-TG to drive SI discussion and test specification for UHS-II (SD4.0).

Catch our webinar "Understanding and Optimizing Equalizers (EQ) in PCI Express®"

PCI Express® (PCIe®) has become the interconnect of choice for data-intensive applications like data center, AI/machine learning, HPC, automotive, IoT, and military/aerospace. In this webinar, we aim to provide you with not only a clearer understanding of how to optimize Equalizers (EQ) in PCI Express® but also practical knowledge through case studies and an opportunity for Q&A.

Who should attend?

This webinar is designed for any engineers involved in IC/system/PCB design or test at entry-level, new to the subject(s), or with a basic foundation who want to learn more. 

We will explore the use of equalizers in SerDes applications and specifically in PCIe:

  • Design challenges with the latest PCIe standards
  • Understanding Equalizers in SerDes applications
  • Using CTLE, DFE, and FFE
  • Equalization Techniques For PCIe Link Dynamic Equalization
  • PCI Express Equalization Case Study
  • And more!
Published by GRL Team January 30, 2024