Date: June 13, 2023 (Tuesday)
Session 1: 08:00 PDT | 17:00 CEST
Session 2: 18:00 PDT | 09:00 SGT / 北京时间 (June 14)
Speakers
Miki Takahashi - Executive Vice President of Engineering, Granite River Labs
Miki is an industry veteran with decades of IC development experience and currently chairs the SD Card Association’s UHS-TG.
Barbara Aichinger - Vice President New Business Development, FuturePlus Systems
Barbara is a JEDEC Committee member (DDR Memory) and is a frequent public speaker on topics of DDR Memory.
Miki is an industry veteran with decades of IC development experience and currently chairs the SD Card Association’s UHS-TG.
Barbara Aichinger - Vice President New Business Development, FuturePlus Systems
Barbara is a JEDEC Committee member (DDR Memory) and is a frequent public speaker on topics of DDR Memory.
Catch our webinar on DDR Validation Demystified:
The Power of Combining Physical Layer and Protocol Testing
Are you struggling to understand physical layer and protocol testing for DDR? To shed light on the benefits of combining physical layer and protocol testing, we are excited to invite you to join our webinar on DDR Validation Demystified: The Power of Combining Physical Layer and Protocol Testing. In this webinar, experts from GRL and FPS will discuss the importance of performing both types of testing.
Don't miss out on this valuable opportunity to improve your DDR testing process!
Topics you will learn from our webinar:
- DDR physical design and validation challenges
- What makes DDR physical design difficult?
- How should DDR timing/parameter be validated?
- DDR system electrical bench test
- Why verify the DDR protocol rules
- What is DDR protocol memory?
- Protocol violation
- Row hammer
- How to probe the target for protocol violation testing
- Q&A
Note: In the event that you are unable to join either session, please also sign up on our registration page and we will send you the recording after the webinar ends.
