Senior FPGA Design Engineer - Bangalore (GRLIN202207008)

GRL seeks a full-time Senior FPGA Design Engineer - Bangalore

Date:  July 18, 2022
City:  Bangalore, India
Position code: GRLIN202207008

About GRL

Headquartered in Silicon Valley with over 350 staff in 9 countries, GRL is the world leader in testing and related engineering services to help hardware product developers integrate the latest digital connectivity and smart charging technologies. GRL is a unique and exceptional institution. We serve customers of all sizes from a diverse range of industries including bleeding-edge cloud computing, mobile, and autonomous driving. We support product development at all stages of the value chain, from chips to end products, and help our customers validate the full system stack, from physical layer to protocol to application layer to ensure robust performance and interoperability.

We do much more than test: we guide, consult, analyze, troubleshoot, and present useful insights to help our customers improve product performance and ensure successful market adoption. We work closely with early adopters, standards committees, and leading test equipment manufacturers to develop test methodologies and early test solutions, providing “glue” that brings technology ecosystems together. We stay at the forefront of these technologies and bring insiders' know-how and hands-on expertise to our customers. Maintaining our leadership requires staying at the technical leading edge, a relentless focus on execution and quality, and, most importantly, the very best people.

GRL offers competitive salary and benefits.

About the role

As a Sr. FPGA Design Engineer, you will be a valued member of the FPGA core design team.

Role and Responsibilities:

  • Involve in design and system architecture for complex FPGA based Test solutions
  • Develop Verilog code for various system blocks
  • Participate in size/ timing optimization of complete FPGA design
  • Place & route flows, pinning, and timing optimization for Xilinx and/ or Altera
  • Continuously improving test and simulation environment to assure FPGA design works
  • Good hardware debugging capability using industry-standard test equipment like Protocol Generator/ILA/Scope/Signal Analyzer/chip scope, etc.
  • Work on serial protocols such as I2C, SPI, UART, 10G-Ethernet, USB 3.0, SATA, PCIe, Display Port, etc.
  • Must be capable to understand and work on high-speed memory interfaces and develop glues logic
  • Must independently work on the RTL design, simulation and verification of the developed modules
  • The role includes RTL design, verification, FPGA partitioning and testing on the actual hardware
  • Responsible for ownership of emulation of a block/subsystem on emulation platforms
  • You will work with Firmware, software and product verification teams to validate and debug the functionality.

Qualifications:

  • Bachelor’s degree in Electronics
  • 5 - 8 yrs of experience

Specific skills:

  • RTL design using Verilog, Xilinx Vivado ISE, Intel Quartus Prime tools
  • Excellent communication and interpersonal skills
  • Strong and effective presentation skills
  • Self-motivated
  • Take ownership of problems
  • Creative problem solving
  • Team player

 

GRL is an Equal Opportunity Employer.
Submit your CV to careers@graniteriverlabs.com.