Demystifying PCIe® Electrical, Link and Protocol Design & Test (Webinar Recording, PDF Presentation) | GraniteRiverLabs

Topics:

• PCIe overview and design considerations
  • Base vs CEM specifications
  • Reference channel and EQ considerations
  • Design for testability – addressing the “gotchas” including CEM and test board design
• PCIe compliance test requirements overview – Base vs CEM
  • Electrical and link equalization
  • Link and transaction layer
  • Lane margining
  • Config space and interoperability
  • Certification / Integrator List requirements
• Electrical & link EQ setup considerations and pitfalls
  • Calibration, test channel characterization, form factors & fixtures, etc.
  • Debugging case study
  • When “testing by the book” isn’t practical – case study for embedded / chip-to-chip
• Link, transaction and system layer design and test
  • Design and test considerations
  • Test and debugging solutions
  • PCIe system performance analysis and benchmarking
  • CXL: what is it, how does it leverage PCIe, and why should you care
• and more!