SerDes & Signal Integrity In-Person Trainings

SerDes & SI Training eventbrite

Session 1: 17 May, 2023 | 1:00 PM - 5.30 PM (PST)
Session 2: 18 May, 2023 | 9:00 AM - 3:00 PM (PST)

Location: Granite River Labs Inc | 3000 Lakeside Drive, Santa Clara, CA, 95054

Instructor:

Miki Takahashi - EVP of Engineering and Lead SerDes and Signal Integrity Expert

Want to learn about the fundamentals of SerDes and Signal Integrity?

Join GRL for a valuable learning experience at our headquarters. Attend two technical classes on complementary subjects, held back-to-back in an in-person setting.

Who should attend?

Engineers involved in IC/system/PCB design or test at entry-level, new to the subject(s), or with a basic foundation who want to learn more.

Fee per attendee

One session $750 (USD), both sessions $1350 (USD). Group discounts are available. Contact qanderson@graniteriverlabs.com to inquire.

Our instructor

Miki has extensive experience in SerDes IP development and integration into ICs and systems, and has helped hundreds of GRL customers to improve SerDes and Signal Integrity design performance in their products. Prior to GRL, Miki spent 15 years at O2Micro, Advanced Chip Express and NEC (now Renesas) as analog design manager. Miki earned a master's in material physics from Nagoya University.

Miki currently serves as:

Co-chair of Open Alliance TC13
Chair of SD Card Association UHS Task Group
Technical contributor to PCI-SIG and Automotive SerDes Alliance

What can you expect to learn in our technical classes?

May 17
Wednesday
1:00 PM - 5:30 PM (PST)

Session 1: Fundamentals of Serial/Deserializers (SerDes) in Digital Applications

May 18
Thursday
9:00 am - 3:00 pm (PST)
Lunch provided

Session 2: Signal Integrity Design and Test Fundamentals

We will explore SerDes basics, explore how SerDes are used in different connectivity standards and applications, and system cost, performance, and efficiency considerations.

SerDes architecture overview
Clocking, timing, latency, and data encoding schemes (8b/10b etc.)
Transmitters and Receivers – preemphasis and deemphasis, drive, gain, taps, equalization (EQ) schemes, phase-locked loop (PLL), Clock Data Recovery (CDR), and skip order set
Signal modulation schemes - NRZ vs PAM
Physical media considerations: twisted pair (BASE-T) vs coax, optical vs copper
Signal integrity design challenges
SerDes test basics and the evolution of faster and faster data rates

We will explore key Signal Integrity (SI) design and test principles including: